1. Field of the Invention
This invention relates to high-speed, high-resolution current mode D/A converters (DACs) converting digital signals into analog signals.
2. Description of the Related Art
Conventional high-speed current mode D/A converters (DACs) of binary switched current mode type, segmented type, and combination type of the two are known. DACs of the binary switched type include many unit current cells. The unit current cell are grouped to sets of a single cell, two cells, four cells, . . . 2nxe2x88x921 cells. The current cells in each group turn on or off together. When an n-bit input digital word is processed, according to the value of each bit in the digital word, the corresponding groups of current cells turn on or off. An output current is usually supplied to a resistor having a small resistance of 50 or 75 ohms, generating the corresponding output voltage. FIG. 6 shows a simplified diagram for such a DAC.
In FIG. 6, a first group 101 comprises one current cell, a second group 102 two current cells, a third group 103 four current cells, and so on. That is to say, the number of current cells in each group doubles moving from one group to the next group. Each of switches S1, S2, S3, . . . sends current from the corresponding current cell group to output. Each of switches S1xe2x80x2, S2xe2x80x2, S3xe2x80x2, . . . connects the same group to the ground so that it will not take time to return to normal operating conditions after forcing current sources to turn completely off. The switches are also split into groups 111, 112, 113, etc. Each group includes a pair of switches. These switch groups correspond to the current cell groups. When S1 is on, LSB (Least Significant Bit) is 1; when S2 is on, the second LSB is 1; when S3 is on, the third LSB is 1. Similarly, when Sn is on, MSB (Most Significant Bit) is 1; when Snxe2x88x921 is on, the second MSB is 1.
Such a current mode DAC has the disadvantage of difficult matching the currents from groups of current cells with binary weights. A 10-bit DAC would need 1,023 unit current cells. Each group can be viewed as a differential pair called a current steering cell.
While such a DAC has the advantage of very simple logic circuit structure, it has the disadvantages of large glitches which are noise signals occurring at the time of switching, and significant non-linearity caused by mismatches among binary sets of current cells. Such a system is often called a xe2x80x9cbinary current mode DAC.xe2x80x9d
Other circuits called xe2x80x9csegmented current mode DACsxe2x80x9d are known. The advantage of this type of DACs over the conventional one is considerably improved linearity and a significantly smaller glitch power. Circuits of this type also comprise many unit current cells. These unit current cells 121 comprise a combination of a current source and two switches. One circuit shown in FIG. 7 is a single-ended single current cell 121 and corresponds to one digital signal. The circuit shown can be considered to be one for LSB directly corresponding to the digital signal. In such a segmented current mode DAC, the unit current cells 121 are turned on and off one by one, not as a group. An input n-bit data signal is converted into 2nxe2x88x921 digital signals by a logic circuit. Individual digital signals generated as a result of this conversion turn the unit current cells on and off. This decoder logic circuit for converting an n-bit signal into 2nxe2x88x921 signals covers a very large hardware area and consumes a large amount of power.
In a high-resolution DAC having a large value of n, therefore, circuits of the above binary current cells and segmented type are usually combined to reduce the size of the required hardware. However, this compromises accuracy and enlarges signal glitches. Moreover, many unit current cells are used, and so there have been the problems of complex circuit layout and need for large areas.
These problems with the conventional art arose chiefly from turning on and off current cells discontinuously. In other words, conventional current mode DACs have had the problem of 100% of an electric current from current cells being sent either to an output or to the other output in the case of differential type DACs (or to the ground for single-ended DACs). Therefore, a current cell or a differential pair in each current cell will receive very strong signals at its input and be exposed to large current fluctuations at the xe2x80x9ccommon sourcexe2x80x9d point of differential pairs, resulting in large glitches and significant non-linearity.
An object of the present invention is to provide a new circuit structure in order to resolve the above problems.
The present invention provides a high-speed current mode DAC comprising a combination of a resistor-type DAC circuit including a digital decoder circuit and a highly linear transconductor.
In a current mode DAC according to the present invention, differential pairs or transconductors are not turned on or off completely. That is to say, the present invention makes active use of several transconductor states in a predetermined range. In the whole range of input, individual differential pairs can take any of states distributed discretely from one end of the range to the other end of the range. In this limited sense the current mode DAC according to the present invention adopts an analog-like approach. Moreover, fluctuations in the voltage input to each transconductor are relatively small, resulting in a significant reduction of glitches in question.
The present invention also provides a novel highly linear transconductor. This transconductor has high linearity by making use of two differential pairs each one of which does not necessarily have high linearity or linearity comparable to that of the resulting transconductor.
More specifically, the present invention provides: (1) a current mode D/A converter comprising a resistor-type D/A converter circuit having a digital decoder circuit which accepts a digital input signal, a plurality of series-connected resistors of which nodes are connected to a plurality of output terminals of the resistor-type D/A converter circuit through a plurality of switches which are turned on and off according to outputs from the digital decoder circuit; and a highly linear transconductor for receiving a voltage output from the resistor-type D/A converter circuit and providing an analog current output; (2) a transconductor comprising a first MOS transistor differential pair and a second MOS transistor differential pair connected in parallel to each other at their outputs with their polarities of input voltages reversed and having different transconductance values and different current sources connected to the first and second transistor differential pairs respectively, wherein signal voltages which are proportional to input digital signal voltages but have different values are applied to the first and second transistor differential pairs; and (3) a current mode D/A converter described in (1) which uses the transconductor described in (2) above.
Such transconductors can be manufactured using either of the bipolar or CMOS technology. When actually implemented, MOS transistors are preferably used. The first differential pair can preferably be formed by combining a plurality of differential pairs each of which can have the same parametric characteristics as those of the second differential pair. When the first differential pair is formed of a plurality of differential pairs which have the same parametric characteristics as the second pair and which are connected in parallel with each other, matching would be considerably facilitated, resulting in smaller errors.
Also, one resistor-type D/A converter circuit and a plurality of transconductors may be included in the current mode D/A converter of the present invention. In this preferred case, the single resistor-type D/A converter circuit can include a k-bit resistor-type D/A circuit to process a n-bit digital signal, where n is more than k. This is made possible, for example for a 12-bit digital signal, by using different portions of a single 7-bit resistor-type DAC circuit.
Furthermore, a plurality of [one] resistor-type D/A converter circuits and a plurality of transconductors may be included in the current mode D/A converter of the present invention. These resistor-type D/A converter circuits and transconductors form a plurality of pairs and each of these pairs can perform D/A conversion on a plurality of bits included in an n-bit digital signal input. For example, a 10-bit input would be divided in two (5 bits per pair), a 12-bit input in three (4 bits per pair), and a 15-bit input in three (5 bits per pair), or any other combinations.
In the above transconductor, the ratio of transconductance of the first MOS transistor differential pair to that of the second MOS transistor differential pair may be substantially eight to one, and the ratio of a signal voltage input to the first MOS transistor differential pair to the input to the second MOS transistor differential pair may be substantially one to two. In this case, the capacity of the current source connected to the first transistor differential pair may be eight times that of the current source connected to the second transistor differential pair. Preferably, the current source for the first pair may be formed of eight current sources each of which has the same characteristics as those of the current source for the second transistor differential pair and which are connected in parallel with each other, just like the first differential pair in the transconductor can be formed of several transistor pairs in which each transistor has the same parametric characteristics as those used in the second differential pair as discussed above. Again, matching would be easier if the same unit transistors are used to form current sources of differing capacities.